Introducing Quadmachine II

Quadmachine is a virtual instruction set architecture, designed mainly as a target for simple educational compilers. It has the following noteworthy features:

  • RISC design
  • word size 64 bits
  • address size 64 bits (theoretical maximum memory size 16 exabytes)
  • all memory access is in word units
  • 65534 general-purpose 64-bit registers
  • 2 additional special-purpose 64-bit registers
  • a variant of the “register windows” technique with automatic spilling

All of these, except for the preposterously large register file, are more or less realistic for a 64-bit RISC design. The size of the register file is intended to trivialize register allocation in compilers.

This is the second Quadmachine design. Main differences from the previous design are a move to a load-store RISC architecture and the upgrade of the word size to 64 bits.

There is a software realization of the Quadmachine architecture, with a graphical debug console. It is written in Java for portability; speed was not an implementation concern.

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3 thoughts on “Introducing Quadmachine II”

  1. If you ever get the urge to write about it, I’d be interested in reading how the implementation happened.

  2. I was thinking about the components and their implementation order. The first darcs commit already shows interfaces and implementations for registers, memory, assembler and a segmentation fault. This is already a pretty large package, what did you start with? Did you ever have to backtrack on any decisions?

    Reading through the repository is sort of like reading through a completed mathematical proof – it shows how it’s made correctly, but it lacks human insight ūüôā

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