Quadmachine is a virtual instruction set architecture, designed mainly as a target for simple educational compilers. It has the following noteworthy features:
- RISC design
- word size 64 bits
- address size 64 bits (theoretical maximum memory size 16 exabytes)
- all memory access is in word units
- 65534 general-purpose 64-bit registers
- 2 additional special-purpose 64-bit registers
- a variant of the “register windows” technique with automatic spilling
All of these, except for the preposterously large register file, are more or less realistic for a 64-bit RISC design. The size of the register file is intended to trivialize register allocation in compilers.
This is the second Quadmachine design. Main differences from the previous design are a move to a load-store RISC architecture and the upgrade of the word size to 64 bits.
There is a software realization of the Quadmachine architecture, with a graphical debug console. It is written in Java for portability; speed was not an implementation concern.